The George Washington University

Associate Professor
Department of Electrical and Computer Engineering
The George Washington University
Science and Engineering Hall
800 22nd St Suite 6600 NW
Washington DC 20052
Phone:202-994-2980
Fax :202-994-0227


Awards and Honors

GWU SEAS Faculty Recognition Award, 2012

NSF Faculty Early CAREER Award, 2012

Best Poster Award, IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT), 2011

ORAU Ralph E. Powe Junior Faculty Enhancement Award, 2010

GWU UFF/Dilthey Faculty Fellowship, 2009

Senior Member, IEEE and ACM


Research

My area of research is computer architecture. I am especially interested in issues concerning multi-cores like performance, power, application debugging and security.


Research Sponsors



Publications

Fan Yao, Yongbo Li, Yurong Chen, Hongfa Xue, Tian Lan, Guru Venkataramani, StatSym: Vulnerable Path Discovery through Statistics-guided Symbolic Execution, Proceedings of 47th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2017, Denver, CO (accepted 49 out of 220 submissions) [pdf].

Fan Yao, Jingxin Wu, Suresh Subramaniam and Guru Venkataramani,WASP: Workload Adaptive Energy-Latency Optimization in Server Farms using Server Low-Power States, Proceedings of 10th IEEE International Conference on Cloud Computing (IEEE CLOUD), 2017, Honolulu, HI (acceptance rate= 18%) [pdf].

Fan Yao, Guru Venkataramani, Milos Doroslovacki, Covert Timing Channels Exploiting Non-Uniform Memory Access based Architectures, Proceedings of 27th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI), 2017, Banff, Canada. (accepted 48 out of 197 submissions) [pdf]

Hongfa Xue, Yurong Chen, Fan Yao, Yongbo Li, Tian Lan, Guru Venkataramani, SIMBER: Eliminating Redundant Memory Bound Checks via Statistical Inference, Proceedings of 32nd International Conference on ICT Systems Security and Privacy Protection (IFIP SEC), 2017, Rome, Italy. (accepted 38 out of 196 submissions) [pdf]

Yongbo Li, Yurong Chen, Tian Lan, Guru Venkataramani, MobiQoR: Pushing the Envelope of Mobile Edge Computing via Quality-of-Result Optimization , Proceedings of 37th IEEE International Conference on Distributed Computing Systems (ICDCS) Applications and Experiences Track, 2017, Atlanta, GA. [pdf]

Jie Chen, Guru Venkataramani, enDebug: A hardware-software framework for automated energy debugging, Journal of Parallel and Distributed Computing - Elsevier, 96: 121-133 (2016) [pdf]

Guru Venkataramani, Jie Chen, Milos Doroslovacki, Detecting Hardware Covert Timing Channels, IEEE Micro 36(5): 17-27 (2016). [pdf]

Yongbo Li, Fan Yao, Tian Lan, Guru Venkataramani, SARRE: Semantics-Aware Rule Recommendation and Enforcement for Event Paths on Android, IEEE Trans. Information Forensics and Security 11(12): 2748-2762 (2016). [pdf]

Fan Yao, Jingxin Wu, Guru Venkataramani, Suresh Subramaniam, A Dual Delay Timer Strategy for Optimizing Server Farm Energy, IEEE CloudCom, 2015, Vancouver, BC. [pdf]

Yongbo Li, Fan Yao, Tian Lan, Guru Venkataramani, POSTER: Semantics-Aware Rule Recommendation and Enforcement for Event Paths, SecureComm 2015, Dallas, TX. [pdf]

Jie Chen, Guru Venkataramani, A Hardware-Software Cooperative Approach for Application Energy Profiling, IEEE Computer Architecture Letters 14(1), 5-8 (2015) [pdf]

Jie Chen, Guru Venkataramani, CC-Hunter: Uncovering Covert Timing Channels on Shared Processor Hardware, Proceedings of Forty Seventh Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-47), 2014, Cambridge, UK. [pdf]

Jie Chen, Guru Venkataramani, An Algorithm for Detecting Contention-Based Covert Timing Channels on Shared Hardware, Proceedings of the Third Annual Workshop on Hardware and Architectural Support for Security and Privacy held in conjunction with ISCA 2014, Minneapolis, MN. [pdf]

Fan Yao, Jingxin Wu, Guru Venkataramani, Suresh Subramaniam, A Comparative Analysis of Data Center Network Architectures, Proceedings of the IEEE International Conference on Communications - Next Generation Networking, 2014, Sydney, Australia. [pdf]

Jie Chen, Guru Venkataramani, H Howie Huang, Exploring Dynamic Redundancy to Resuscitate Faulty PCM Blocks, ACM Journal on Emerging Technologies in Computing Systems (ACM JETC), May 2014 [pdf]

Jie Chen, Fan Yao, Guru Venkataramani, Watts-inside: A Hardware-Software Cooperative Approach for Multicore Power Debugging, Proceedings of the Thirty First IEEE International Conference on Computer Design, Asheville, NC. (ICCD'13) [pdf]

Fan Yao, Jie Chen, Guru Venkataramani, JOP-alarm: Detecting Jump-oriented Programming-based anomalies in applications, Poster in the Proceedings of the Thirty First IEEE International Conference on Computer Design, Asheville, NC. (ICCD'13)[pdf]

Jie Chen, Guru Venkataramani, H Howie Huang, RePRAM: Recycling PRAM Faulty Blocks for Extended Lifetime, Proceedings of the Forty second IEEE International Conference on Dependable Systems and Networks, Boston, MA. (DSN'12) [pdf]

Jie Chen, Guru Venkataramani, Gabriel Parmer, The Need for Power Debugging in the Multi-Core Environment, IEEE Computer Architecture Letters (CAL), 12 Jan. 2012. IEEE computer Society. [pdf]

Ioannis Doudalis, James Clause, Guru Venkataramani, Milos Prvulovic, Alessandro Orso, Effective and Efficient Memory Protection Using Dynamic Tainting, IEEE Transactions on Computers (TC), IEEE Transactions on Computers, Vol. 61, No. 1, January 2012.[pdf]

Jie Chen, Ron Chiang, H Howie Huang, Guru Venkataramani, Energy-Aware Writes to Non-Volatile Main Memory, Proceedings of the 4th Workshop on Power-Aware Computing and Systems, Cascais, Portugal (HotPower'11). [pdf] Selected as "Best Of HotPower'11" to appear in ACM Operating Systems Review

Jie Chen, Zachary Winter, Guru Venkataramani, H Howie Huang, rPRAM: Exploring Redundancy Techniques to Improve Lifetime of PCM-based Main Memory, Poster session of The Twentieth International Conference on Parallel Architectures and Compilation Techniques (PACT), Galveston Island, TX. [pdf] Best Poster Award

Guru Venkataramani, Christopher J Hughes, Sanjeev Kumar, Milos Prvulovic, DeFT: Design Space Exploration for On-the-Fly Detection of Coherence Misses, ACM Transactions on Architecture and Code Optimization (TACO), July 2011. [pdf]

Jungju Oh, Christopher J Hughes, Guru Venkataramani, Milos Prvulovic, LIME: A Framework for Debugging Load Imbalance in Multi-threaded Execution, To appear in the Thirty third International Conference on Software Engineering, Honolulu, HI (ICSE'11) [pdf].

Guru Venkataramani, Christopher J. Hughes, Sanjeev Kumar, Milos Prvulovic, Coherence Miss Classification For Performance Debugging in Multi-Core Processors, Thirteenth Workshop on Interaction between Compilers and Computer Architecture (Interact-13), Raleigh, NC held in conjunction with HPCA'09. [pdf]

Guru Venkataramani, Ioannis Doudalis, Yan Solihin, Milos Prvulovic, MemTracker: An Accelerator for Memory Debugging and Monitoring, ACM Transactions on Architecture and Code Optimization (TACO), Volume 6 Issue 2, June 2009.[pdf]

Guru Venkataramani, Ioannis Doudalis, Yan Solihin, Milos Prvulovic, FlexiTaint: A Programmable Accelerator for Dynamic Taint Propagation , Fourteenth International Symposium on High Performance Computer Architecture, Salt Lake City, UT (HPCA '08). [pdf]

Guru Venkataramani, Brandyn Roemer, Yan Solihin, Milos Prvulovic, MemTracker: Efficient and Programmable support for Memory Access Monitoring and Debugging, Thirteenth International Symposium on High Performance Computer Architecture, Phoenix, AZ (HPCA '07). [pdf]

Jianli Shen, Guru Venkataramani, Milos Prvulovic, Tradeoffs in Fine-grained Heap Memory Protection, Workshop on Architectural and System Support for Improving Software Dependability (ASID), San Jose, CA held in conjunction with ASPLOS'06. [pdf]

Mazen Kharbutli, Xiaowei Jiang, Yan Solihin, Guru Venkataramani, Milos Prvulovic, Comprehensively and Efficiently Protecting the Heap, Appears in the Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, CA (ASPLOS'06). [pdf]

Guru Venkataramani, Hemanth Manoharan, Ranjani Parthasarathi, Fetch Bottleneck and Branch Penalty Reduction using 2 Instruction Queues, In the Poster Session of Tenth International Conference on High Performance Computing, Hyderabad, India (HiPC'03). [pdf]