Homework #3

Full Adder Operation and Layout:

Design, simulate and verify the operation of a 4-bit full adder circuit.
Employ the following test vectors:

1010 + 1100
0110 + 1001
1111 + 1111
0000 + 0001
1111 + 1000
1100 + 1011

Also generate the layout for the circuit using L-Edit. Employ the
mhp_n05d.tdb technology file.