The George Washington University
School of Engineering and Applied Science
Department of Electrical and Computer Engineering
 ECE 20 - Summer 2000

Experiment # 6

BJT Detailed Analysis on
Common Emitter and Common Collector






Equipment:
You must make up a complete equipment list and have your instructor review it before you start.
 

Objectives:

Figure # 1


1.- (HW) CEC Analysis

In Exp. #5, the DC Bias Analysis and general formula for Unloaded Voltage Gain (Avo) for circuit of Figure #1 were conducted.  The more detailed analysis analysis on Common Emitter Amplifier for this circuit will be conducted in this section.

When this circuit is operated in CEC:

    1. Find ROUT
    2. RIN
    3. Unloaded Voltage Gain, Avo
    4. Av (RL=ROUT)
    5. Ai (RL=ROUT).
    6. Maximum input voltage vin max that the amplifier can accept before the output distorts (Unloaded case).
To get a credit for this analysis, you must show all the steps below:
1.  Do DC Bias Analysis
2.  Draw Small Signal Equivalent circuit for CEC
3.  Find Rin, then Rout @Vin=0
4.  Find Vout and Vin to get Av
5.  Find Av @ RL=Rout
6.  Find Ai
7.  Find Vinmax
 
 

2.- CEC Verification

Build and fully test the circuit shown in Figure #1. By applying a sinusoidal signal such that the small signal approximation holds, measure:

    1. RIN (input impedance) and ROUT (output impedance) of the assembled circuit.

      2.  
    2. Unloaded Voltage gain, Avo.  Label the plot - "Plot 2a - Avo for CEC"

      3.  
    3. Voltage Gain for RL equal to 2*ROUT, ROUT, ROUT /2, and ROUT /4.  Print the output plot for each RL and label each of plot as Plot 2b -  "Av @ RL=__ for CEC"

      4.  
    4. Find the maximum input voltage that the amplifier can accept before the output distorts (Unloaded case). Print the plot and label it as "Plot 2c - Vin max before output distorts for CEC"

      5.  
    5. Determine the phase relationship between the input and output voltages.

 
 

3.- (HW) CCC Analysis

In Exp. #5, the DC Bias Analysis and general formula for Unloaded Voltage Gain (Avo) for circuit of Figure #1 were conducted.  The more detailed analysis analysis on Common Collector Amplifier for this circuit will be conducted in this section.

When this circuit is operated in CCC:

    1. Find ROUT
    2. RIN
    3. Unloaded Voltage Gain, Avo
    4. Av (RL=ROUT)
    5. Ai (RL=ROUT).
    6. Maximum input voltage vin max that the amplifier can accept before the output distorts (Unloaded case).
To get a credit for this analysis, you must show all the steps below:
1.  Do DC Bias Analysis
2.  Draw Small Signal Equivalent circuit for CCC
3.  Find Rin, then Rout @Vin=0
4.  Find Vout and Vin to get Av
5.  Find Av @ RL=Rout
6.  Find Ai
7.  Find Vinmax
 

4.- CCC Verification

Build and fully test the circuit shown in Figure #1. By applying a sinusoidal signal such that the small signal approximation holds, measure:

    1. RIN (input impedance) and ROUT (output impedance) of the assembled circuit.

      2.  
    2. Unloaded Voltage gain, Avo.  Label the plot - "Plot 4a - Avo for CCC"

      3.  
    3. Voltage Gain for RL equal to 2*ROUT, ROUT, ROUT /2, and ROUT /4.  Print the output plot for each RL and label each of plot as Plot 4b -  "Av @ RL=__ for CCC"

      4.  
    4. Find the maximum input voltage that the amplifier can accept before the output distorts (Unloaded case). Print the plot and label it as "Plot 4c - Vin max before output distorts for CCC"

      5.  
    5. Determine the phase relationship between the input and output voltages.

 
 

5.- Conclusion

  1. What can you say about the general characteristics of CEC amplifier( Rin, Rout, Av, Ai etc).
  2. What can you say about the general characteristics of CEC amplifier( Rin, Rout, Av, Ai etc).
  3. Compare the measured results to your analysis for both CE and CC. Explain any differences.
  4. Why is there a difference between the value the function generator was set for and the actual input signal?
      5.