Extraction of Layout and Layout Simulation 

a)  Generate the layout for the four bit full adder employing TGateCE that was designed in Homework #6. 
Note: Use all the components from AnaCMOS library to design the circuit in S-Edit.  Employ the mhp_n08a.tdb technology file to generate the layout. 

b)  Perform extraction procedure to produce the SPICE extract output file ( *.sp file).  Add appropriate lines in this  file to simulate  the following operations:

Y1 = A + B
Y2 = B + C
Y3 = A + C

where A = [1001], B = [1000] and C = [1100].  Verify the results.  Also, Attach the SPICE extract output file with your report.

c)  Change the values of all the parasitic capacitances (Cpar) in the SPICE extract output file to 100 times its original values.  Repeat part (b).  Note any changes in the waveforms.