Gate Delay and Average Power Dissipation

In this exercise, we will learn how to calculate average gate delay and average power dissipation (Reference: Sedra & Smith, Secs. 13.1 and 13.2 plus lecture notes). 

Consider the two-input CMOS NAND gate (NAND2C) from the SCMOS library. Employ the model file ml2_125.md given in the previous homeworks. Perform time-domain simulations in order to calculate the average gate delay and dynamic power dissipation under the following conditions: 
          
1.Sweep the power supply VDD according to: {3.0, 3.5, 4.0, 4.5, 5.0} Volts. 
2.Fix one input of the two-input NAND gate to high. 
3.Apply a rectangular input signal fo the second input with frequency 1 MHz and zero rise/fall-times. 
4.Connect the NAND2C to a capacitor load of 4.8 pF. 
5.Plot the transient simulation results for the output voltage and the current from the voltage source. 
 

Based on these results 

1.Compute the gate delays (tpLH, tpHL and tP) and compare them with the  formulae given in the textbook. 
2.Compute the average power dissipation (over one period of the input) and compare them with the formulae given in the textbook. 
3.Present a summary of your computational results and comparisons in a table.