0
-48.95,84.0647,173.681,-40.554
214
VE_PMOS
-31,41.5
T_ctrl100
T_in101
T_in299
angle 90
DEFAULT_DELAY 1
216
VA_NMOS
-31,36
T_ctrl100
T_in98
T_in2101
angle 90
DEFAULT_DELAY 1
218
EE_VDD
-30,46.5
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 1
220
FF_GND
-30,32
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 0
222
AA_TOGGLE
-39.5,38
CLICK_BOX -0.76,-0.76,0.76,0.76
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 1
224
GA_LED
-21.5,38.5
N_in0101
LED_BOX -0.76,-0.76,0.76,0.76
angle 0.0
226
AA_LABEL
-42,35.5
LABEL_TEXT Input A
TEXT_HEIGHT 1
angle 0.0
228
AA_LABEL
-16.5,38.5
LABEL_TEXT Output B
TEXT_HEIGHT 1
angle 0.0
230
AA_LABEL
-24.5,31
LABEL_TEXT Ground ( 0 )
TEXT_HEIGHT 1
angle 0.0
232
AA_LABEL
-25,47
LABEL_TEXT Power ( 1)
TEXT_HEIGHT 1
angle 0.0
234
AA_LABEL
-20,51
LABEL_TEXT The NOT Gate using CMOS transistors
TEXT_HEIGHT 2
angle 0.0
236
AA_LABEL
-14,43.5
LABEL_TEXT p-Type Transistor closes when input =0
TEXT_HEIGHT 1
angle 0.0
238
AA_LABEL
-14.5,42
LABEL_TEXT and then path from power to output B
TEXT_HEIGHT 1
angle 0.0
240
AA_LABEL
-14.5,35.5
LABEL_TEXT n-Type Transistor closes when input=1
TEXT_HEIGHT 1
angle 0.0
241
AA_LABEL
-10.5,34
LABEL_TEXT and then path from ground to output B
TEXT_HEIGHT 1
angle 0.0
98
0
-30,33,-30,35
216
T_in
220
OUT_0
99
0
-30,42.5,-30,45.5
214
T_in2
218
OUT_0
100
0
-35,36,-35,41.5
36 3
38 1
41.5 2
1
-37.5,38,-35,38
222
OUT_0
-35 0
2
-35,41.5,-33,41.5
214
T_ctrl
-35 0
3
-35,36,-33,36
216
T_ctrl
-35 0
101
0
-30,37,-30,40.5
216
T_in2
214
T_in
38.5 1
1
-30,38.5,-22.5,38.5
224
N_in0
-30 0
-9.4,45.905,53.25,10.8364
9
AA_LABEL
18,42.5
LABEL_TEXT Which gate is being implemented ?
TEXT_HEIGHT 2
angle 0.0
209
AA_LABEL
37.5,21.5
LABEL_TEXT If one of the bottom two closes
TEXT_HEIGHT 1
angle 0.0
210
AA_LABEL
39.5,20
LABEL_TEXT then connection to ground and C=0
TEXT_HEIGHT 1
angle 0.0
211
AA_LABEL
33,33.5
LABEL_TEXT If both upper two transistors close
TEXT_HEIGHT 1
angle 0.0
212
AA_LABEL
33.5,32
LABEL_TEXT then connection to power and C=1
TEXT_HEIGHT 1
angle 0.0
33
VE_PMOS
17.5,33
T_ctrl16
T_in7
T_in217
angle 90
DEFAULT_DELAY 1
35
VE_PMOS
17.5,28
T_ctrl15
T_in8
T_in27
angle 90
DEFAULT_DELAY 1
37
VA_NMOS
15.5,21
T_ctrl16
T_in18
T_in28
angle 90
DEFAULT_DELAY 1
39
VA_NMOS
23,21
T_ctrl15
T_in18
T_in28
angle 90
DEFAULT_DELAY 1
41
AA_TOGGLE
9,33
CLICK_BOX -0.76,-0.76,0.76,0.76
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 0
43
AA_TOGGLE
9,28
CLICK_BOX -0.76,-0.76,0.76,0.76
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 0
45
AA_LABEL
7,33.5
LABEL_TEXT A
TEXT_HEIGHT 1
angle 0.0
47
AA_LABEL
7,28.5
LABEL_TEXT B
TEXT_HEIGHT 1
angle 0
49
GA_LED
29,26
N_in08
LED_BOX -0.76,-0.76,0.76,0.76
angle 0.0
50
AA_LABEL
28.5,28
LABEL_TEXT C
TEXT_HEIGHT 1
angle 0
52
EE_VDD
18.5,37.5
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 1
54
AA_LABEL
22.5,39.5
LABEL_TEXT Power: 1
TEXT_HEIGHT 1
angle 0.0
57
FF_GND
18.5,15
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 0
60
AA_LABEL
23,14.5
LABEL_TEXT Ground: 0
TEXT_HEIGHT 1
angle 0.0
7
0
18.5,29,18.5,32
35
T_in2
33
T_in
8
1
16.5,24.5,24.5,24.5
16.5 6
18.5 3
24.5 5
3
18.5,24.5,18.5,27
35
T_in
24.5 1
26 10
5
24.5,22,24.5,24.5
22 8
24.5 1
6
16.5,22,16.5,24.5
37
T_in2
24.5 1
8
24,22,24.5,22
39
T_in2
24.5 5
10
18.5,26,28,26
49
N_in0
18.5 3
15
1
11,28,15.5,28
35
T_ctrl
43
OUT_0
12.5 3
3
12.5,17.5,12.5,28
17.5 4
28 1
4
12.5,17.5,21,17.5
12.5 3
21 5
5
21,17.5,21,21
39
T_ctrl
17.5 4
16
1
11,33,15.5,33
33
T_ctrl
41
OUT_0
13.5 3
3
13.5,21,13.5,33
37
T_ctrl
33 1
17
0
18.5,34,18.5,36.5
33
T_in2
52
OUT_0
18
1
16.5,16,24,16
57
OUT_0
16.5 3
24 2
2
24,16,24,20
39
T_in
16 1
3
16.5,16,16.5,20
37
T_in
16 1
128.1,-68.3027,192.375,-104.281
193
VA_NMOS
155,-96.5
T_ctrl96
T_in92
T_in293
angle 90
DEFAULT_DELAY 1
194
AA_TOGGLE
147,-84.5
CLICK_BOX -0.76,-0.76,0.76,0.76
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 1
195
AA_TOGGLE
147,-88.5
CLICK_BOX -0.76,-0.76,0.76,0.76
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 1
196
AA_LABEL
144.5,-84
LABEL_TEXT A
TEXT_HEIGHT 1
angle 0.0
197
AA_LABEL
143.5,-88.5
LABEL_TEXT B
TEXT_HEIGHT 1
angle 0
198
GA_LED
167.5,-88.5
N_in097
LED_BOX -0.76,-0.76,0.76,0.76
angle 0.0
199
AA_LABEL
167,-85.5
LABEL_TEXT C
TEXT_HEIGHT 1
angle 0
200
EE_VDD
156,-79.5
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 1
201
AA_LABEL
160,-75
LABEL_TEXT Power: 1
TEXT_HEIGHT 1
angle 0.0
202
FF_GND
156,-100.5
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 0
203
AA_LABEL
160.5,-100
LABEL_TEXT Ground: 0
TEXT_HEIGHT 1
angle 0.0
204
EE_VDD
163,-79.5
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 1
205
AA_LABEL
177.5,-80.5
LABEL_TEXT If at least one of the top two closes
TEXT_HEIGHT 1
angle 0.0
206
AA_LABEL
179,-82.5
LABEL_TEXT then connection to power and C=1
TEXT_HEIGHT 1
angle 0.0
207
AA_LABEL
171,-94
LABEL_TEXT If both lower two transistors close
TEXT_HEIGHT 1
angle 0.0
208
AA_LABEL
171.5,-95.5
LABEL_TEXT then connection to ground and C=0
TEXT_HEIGHT 1
angle 0.0
189
AA_LABEL
155.5,-72
LABEL_TEXT Which gate is being implemented ?
TEXT_HEIGHT 2
angle 0.0
190
VE_PMOS
155,-84.5
T_ctrl96
T_in97
T_in291
angle 90
DEFAULT_DELAY 1
191
VE_PMOS
162,-84
T_ctrl95
T_in97
T_in294
angle 90
DEFAULT_DELAY 1
192
VA_NMOS
155,-93
T_ctrl95
T_in93
T_in297
angle 90
DEFAULT_DELAY 1
91
0
156,-83.5,156,-80.5
190
T_in2
200
OUT_0
92
0
156,-99.5,156,-97.5
193
T_in
202
OUT_0
93
0
156,-95.5,156,-94
192
T_in
193
T_in2
94
0
163,-83,163,-80.5
191
T_in2
204
OUT_0
95
0
151,-93,151,-78
-93 1
-84.5 2
-78 3
1
151,-93,153,-93
192
T_ctrl
151 0
2
149,-84.5,151,-84.5
194
OUT_0
151 0
3
151,-78,160,-78
151 0
160 4
4
160,-84,160,-78
191
T_ctrl
-78 3
96
0
150,-96.5,150,-86.5
-96.5 1
-88.5 2
-86.5 3
1
150,-96.5,153,-96.5
193
T_ctrl
150 0
2
149,-88.5,150,-88.5
195
OUT_0
150 0
3
150,-86.5,153,-86.5
150 0
153 4
4
153,-86.5,153,-84.5
190
T_ctrl
-86.5 3
97
0
159.5,-92,159.5,-88.5
-92 4
-88.5 3
3
156,-88.5,166.5,-88.5
198
N_in0
156 7
159.5 0
163 6
4
156,-92,159.5,-92
192
T_in2
159.5 0
6
163,-88.5,163,-85
191
T_in
-88.5 3
7
156,-88.5,156,-85.5
190
T_in
-88.5 3
-48.5125,170.566,66.2875,106.306
2
AA_LABEL
1,119
LABEL_TEXT This is the gate from Page3
TEXT_HEIGHT 1
angle 0.0
242
VE_PMOS
25,137
T_ctrl90
T_in105
T_in2103
angle 90
DEFAULT_DELAY 1
243
VA_NMOS
25,132
T_ctrl90
T_in102
T_in2105
angle 90
DEFAULT_DELAY 1
244
EE_VDD
26,142.5
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 1
245
FF_GND
26,128
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 0
249
GA_LED
36,134.5
N_in0105
LED_BOX -0.76,-0.76,0.76,0.76
angle 0.0
251
AA_LABEL
37.5,131.5
LABEL_TEXT Output D
TEXT_HEIGHT 1
angle 0.0
253
AA_LABEL
30.5,145
LABEL_TEXT This is NOT gate circuit
TEXT_HEIGHT 1
angle 0.0
128
AA_LABEL
5,155.5
LABEL_TEXT Combining gates to build new 'gates'
TEXT_HEIGHT 2
angle 0.0
129
VE_PMOS
2,137.5
T_ctrl89
T_in90
T_in265
angle 90
DEFAULT_DELAY 1
130
VE_PMOS
9,138
T_ctrl88
T_in90
T_in286
angle 90
DEFAULT_DELAY 1
131
VA_NMOS
2,129
T_ctrl88
T_in85
T_in290
angle 90
DEFAULT_DELAY 1
132
VA_NMOS
2,125.5
T_ctrl89
T_in84
T_in285
angle 90
DEFAULT_DELAY 1
133
AA_TOGGLE
-6,137.5
CLICK_BOX -0.76,-0.76,0.76,0.76
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 1
134
AA_TOGGLE
-6,133.5
CLICK_BOX -0.76,-0.76,0.76,0.76
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 1
135
AA_LABEL
-8.5,138
LABEL_TEXT A
TEXT_HEIGHT 1
angle 0.0
136
AA_LABEL
-9.5,133.5
LABEL_TEXT B
TEXT_HEIGHT 1
angle 0
138
AA_LABEL
11.5,136
LABEL_TEXT C
TEXT_HEIGHT 1
angle 0
139
EE_VDD
3,142.5
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 1
140
AA_LABEL
7,147
LABEL_TEXT Power ( 1)
TEXT_HEIGHT 1
angle 0.0
141
FF_GND
3,121.5
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 0
180
EE_VDD
10,142.5
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 1
65
0
3,138.5,3,141.5
129
T_in2
139
OUT_0
84
0
3,122.5,3,124.5
132
T_in
141
OUT_0
85
0
3,126.5,3,128
131
T_in
132
T_in2
86
0
10,139,10,141.5
130
T_in2
180
OUT_0
88
0
-2,129,-2,144
129 1
137.5 2
144 3
1
-2,129,0,129
131
T_ctrl
-2 0
2
-4,137.5,-2,137.5
133
OUT_0
-2 0
3
-2,144,7,144
-2 0
7 4
4
7,138,7,144
130
T_ctrl
144 3
89
0
-3,125.5,-3,135.5
125.5 1
133.5 2
135.5 3
1
-3,125.5,0,125.5
132
T_ctrl
-3 0
2
-4,133.5,-3,133.5
134
OUT_0
-3 0
3
-3,135.5,0,135.5
-3 0
0 4
4
0,135.5,0,137.5
129
T_ctrl
135.5 3
90
0
6.5,130,6.5,133.5
130 4
133.5 3
3
3,133.5,18,133.5
3 7
6.5 0
10 6
18 9
4
3,130,6.5,130
131
T_in2
6.5 0
6
10,133.5,10,137
130
T_in
133.5 3
7
3,133.5,3,136.5
129
T_in
133.5 3
9
18,132,18,137
132 12
133.5 3
137 11
11
18,137,23,137
242
T_ctrl
18 9
12
18,132,23,132
243
T_ctrl
18 9
102
0
26,129,26,131
243
T_in
245
OUT_0
103
0
26,138,26,141.5
242
T_in2
244
OUT_0
105
0
26,133,26,136
242
T_in
243
T_in2
134.5 10
10
26,134.5,35,134.5
249
N_in0
26 0
-61.25,55.1822,3.775,18.7842
13
AE_SMALL_INVERTER
-18,30
IN_053
angle 0.0
DEFAULT_DELAY 1
INPUT_BITS 1
17
AA_AND2
-4.5,34.5
IN_03
IN_14
angle 0.0
INPUT_BITS 2
19
GA_LED
2.5,34.5
N_in05
LED_BOX -0.76,-0.76,0.76,0.76
angle 0.0
98
AA_LABEL
-50.5,49
LABEL_TEXT Examples
TEXT_HEIGHT 2
angle 0.0
100
AA_LABEL
-50.5,44.5
LABEL_TEXT A AND B
TEXT_HEIGHT 2
angle 0.0
102
AA_LABEL
-50,33
LABEL_TEXT A OR B
TEXT_HEIGHT 2
angle 0.0
106
AA_AND2
-14,38.5
IN_052
IN_153
angle 0.0
INPUT_BITS 2
108
AA_TOGGLE
-22.5,40
CLICK_BOX -0.76,-0.76,0.76,0.76
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 1
109
AA_TOGGLE
-22.5,37
CLICK_BOX -0.76,-0.76,0.76,0.76
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 1
110
AE_OR2
-13,29
IN_01
IN_154
angle 0.0
INPUT_BITS 2
111
AA_TOGGLE
-22,27
CLICK_BOX -0.76,-0.76,0.76,0.76
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 0
112
AA_LABEL
-60,40.5
LABEL_TEXT A
TEXT_HEIGHT 2
angle 0.0
113
AA_LABEL
-60,37.5
LABEL_TEXT B
TEXT_HEIGHT 2
angle 0.0
114
AA_LABEL
-59.5,29.5
LABEL_TEXT A
TEXT_HEIGHT 2
angle 0.0
115
AA_LABEL
-59.5,26
LABEL_TEXT B
TEXT_HEIGHT 2
angle 0.0
116
AA_LABEL
-26,40.5
LABEL_TEXT A
TEXT_HEIGHT 2
angle 0.0
117
AA_LABEL
-26,37.5
LABEL_TEXT B
TEXT_HEIGHT 2
angle 0.0
118
AA_LABEL
-26,27.5
LABEL_TEXT C
TEXT_HEIGHT 2
angle 0.0
119
AA_LABEL
-15,45.5
LABEL_TEXT (A AND B) AND ( NOT B OR C)
TEXT_HEIGHT 1
angle 0.0
120
AA_AND2
-47,38.5
IN_056
IN_157
angle 0.0
INPUT_BITS 2
121
AA_TOGGLE
-55.5,40
CLICK_BOX -0.76,-0.76,0.76,0.76
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 0
122
AA_TOGGLE
-55.5,37
CLICK_BOX -0.76,-0.76,0.76,0.76
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 0
123
GA_LED
-38,38.5
N_in055
LED_BOX -0.76,-0.76,0.76,0.76
angle 0.0
124
AE_OR2
-46,27.5
IN_058
IN_159
angle 0.0
INPUT_BITS 2
125
AA_TOGGLE
-55,28.5
CLICK_BOX -0.76,-0.76,0.76,0.76
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 0
126
AA_TOGGLE
-55,25.5
CLICK_BOX -0.76,-0.76,0.76,0.76
angle 0.0
OUTPUT_BITS 1
OUTPUT_NUM 0
127
GA_LED
-36.5,27.5
N_in060
LED_BOX -0.76,-0.76,0.76,0.76
angle 0.0
1
0
-16,30,-16,30
13
OUT_0
110
IN_0
3
0
-9,35.5,-9,38.5
35.5 1
38.5 2
1
-9,35.5,-7.5,35.5
17
IN_0
-9 0
2
-11,38.5,-9,38.5
106
OUT
-9 0
4
0
-8.5,29,-8.5,33.5
29 1
33.5 2
1
-10,29,-8.5,29
110
OUT
-8.5 0
2
-8.5,33.5,-7.5,33.5
17
IN_1
-8.5 0
5
1
-1.5,34.5,1.5,34.5
17
OUT
19
N_in0
52
0
-18.5,39.5,-18.5,40
39.5 1
40 2
1
-18.5,39.5,-17,39.5
106
IN_0
-18.5 0
2
-20.5,40,-18.5,40
108
OUT_0
-18.5 0
53
0
-18.5,37,-18.5,37.5
37 2
37.5 1
1
-18.5,37.5,-17,37.5
106
IN_1
-18.5 0
2
-20.5,37,-18.5,37
109
OUT_0
-20.5 3
-18.5 0
3
-20.5,30,-20.5,37
30 4
37 2
4
-20.5,30,-20,30
13
IN_0
-20.5 3
54
0
-18,27,-18,28
27 2
28 1
1
-18,28,-16,28
110
IN_1
-18 0
2
-20,27,-18,27
111
OUT_0
-18 0
55
1
-44,38.5,-39,38.5
120
OUT
123
N_in0
56
0
-51.5,39.5,-51.5,40
39.5 1
40 2
1
-51.5,39.5,-50,39.5
120
IN_0
-51.5 0
2
-53.5,40,-51.5,40
121
OUT_0
-51.5 0
57
0
-51.5,37,-51.5,37.5
37 2
37.5 1
1
-51.5,37.5,-50,37.5
120
IN_1
-51.5 0
2
-53.5,37,-51.5,37
122
OUT_0
-51.5 0
58
1
-53,28.5,-49,28.5
125
OUT_0
124
IN_0
59
0
-51,25.5,-51,26.5
25.5 2
26.5 1
1
-51,26.5,-49,26.5
124
IN_1
-51 0
2
-53,25.5,-51,25.5
126
OUT_0
-51 0
60
1
-43,27.5,-37.5,27.5
124
OUT
127
N_in0
400.473,49.6836,742.944,-142.016
-120.853,437.392,160.353,279.986
438.225,-85.6101,660.583,-210.076
427.789,298.125,1009.5,-27.4918
649.075,211.912,898.173,72.4787