Schedule of Topics
The course topics are broken down into three parts: the first part
focuses
on processor architectures, the second part focuses on the other
components (memory, I/O) and the third part focuses on multi-core and
multiprocessors. We expect to spend about 10 weeks on the first two
parts. The
relevant chapter in the textbook is listed for each topic.
PART 1: Processor Architectures
- Intro. to computer architectures, models of scalability and
performance models. (Chapter 1)
- Review of Computer Organization, Overview of Instruction
Set Design (Appendix B, Notes) - Self study.
- Instruction-level Parallel Processors (ILP)
- Pipelined processors, Pipeline scheduling (Appendix A,
Notes, Chap. 3): A.1 -- A.6
- Vector Processing (Appendix G) -- Self study.
- Introduction to Superscalar and VLIW/EPIC Processors
- Overview of ILP (Notes).
- Superscalar -- Dynamic scheduling, Branch Prediction
(Chapter 2, Notes).
- VLIW/EPIC processors (Appendix G).
- Summary of ILP and limits (Chapter 3).
PART 2: Components
- Memory Design (Appendix C, Chapter 5)
- I/O System (Chapter 6)
- Optimizing Compilers -- code scheduling for ILP processors
(Notes, Chapter 3, Appendix G).
PART 3: Multiprocessing.
- Intro to Multiprocessing (Chapter 4).
- Multicore processors (Notes, Readings).or Architectures:
SIMD, MIMD, Shared
Memory, Cache Coherence (Chap.6.1)
- Advanced Topics: time permitting
- Embedded systems (Appendix D)
- Reconfigurable architectures (notes)
- Final
Exam - Last Class
- The Final will focus on materials after the midterm,
but will require knowledge of materials before midterm also.
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